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International Journal of Computational and Electronics Aspects in Engineering (IJCEAE)
Volume 7 · Issue 5 · November 2026 · pp. 646–658
Research Article · Peer Reviewed
Received: August 30, 2026 · Accepted: October 27, 2026 · Published: November 10, 2026
DOI: 10.26706/ijceae.7.5.20261009
Open Access · CC BY 4.0

A Leakage-Aware Cross-Layer Analytical Framework for Energy-Efficient Computing: Integrating CMOS Power Modeling, Thermodynamic Constraints, and Energy–Delay Optimization

Mohammed A. Noaman Al-hayanni*
College of Electrical Engineering, University of Technology, Baghdad, Iraq.
ORCID: 0000-0001-6834-211X
*Correspondence: mohammed.a.noaman@uotechnology.edu.iq
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Abstract

The increasing need for high-performance computing within the limits of power has made energy efficiency an important factor in computer designs in recent years. Traditional dynamic voltage and frequency scaling (DVFS) techniques aim to reduce dynamic power consumption by adjusting the voltage. However, too much voltage can lead to high execution delays as well as a higher impact of static leakage energy. Consequently, aggressive low-power operations are not effective in near-threshold computing systems.

In this paper, we propose a leakage-aware model with three layers of computing system abstraction: thermodynamic limits, CMOS power and delay, and architectural performance. The proposed model combines the minimum energy boundary of Landauer's theory with the dynamic and leakage energy of CMOS systems and provides an optimization strategy based on the Energy-Delay Product (EDP). We show a mathematical formula to compare the relationship between the supply voltage, leakage current, threshold voltage, switching activity, and execution delay. The numerical calculations using CMOS technology parameters confirm the presence of an optimal voltage range in which the reduction in dynamic energy is compensated by the delay due to leakage. Sensitivity analysis further shows that variations in leakage current, threshold voltage, and workload characteristics significantly influence the optimal operating point. The proposed framework provides an analytical basis for leakage-aware voltage management and hardware–software co-design strategies in energy-constrained computing systems.

Keywords

Energy-Efficient Computing Cross-layer optimization CMOS Leakage Modeling EDP DVFS Near-Threshold Computing

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